• 姓名: 王桂磊
  • 性别: 男
  • 职称: 副研究员
  • 职务: 
  • 学历: 博士
  • 电话: 010-82995563
  • 传真: 010-82995783
  • 电子邮件: wangguilei@ime.ac.cn
  • 所属部门: 集成电路先导工艺研发中心
  • 通讯地址: 北京市朝阳区北土城西路3号

    简  历:

  • 教育背景

    2001.9-2005.7北京石油化工学院 高分子材料与工程 工学学士

    2006.9 -2009.7 北京大学 集成电路制造与工艺 工程硕士

    2012.9 -2016.7 中国科学院大学 电子通信与工程 工程博士

    工作简历

    2005.7-2009.10 中芯国际集成电路(北京)有限公司 资深工程师

    2009.11-至今 皇家赌场网址hj9990 先导工艺研发中心

    社会任职:

  • 中国科学院青年创新促进会会员

    研究方向:

  • 集成电路工艺与器件,硅光电子器件工艺和集成技术,SiGe、Ge薄膜异质外延生长和ALD 薄膜生长

    承担科研项目情况:

  • 1.中国科学院仪器设备功能开发技术创新项目:用于MOCVD实时监测薄膜晶体质量及厚度的反射率计改造,课题负责人,在研。

    2.国家重点研发计划:高质量硅基半导体量子芯片材料研究,2016YFA0301701,课题负责人,在研。

    代表论著:

  • [1] Guilei Wang, M Moeen, A Abedin, M Kolahdouz, J Luo, C L Qin, H L Zhu, J Yan, H Z Yin, J F Li, C Zhao, H H Radamson,Optimization of SiGe selective epitaxy for source/drain engineering in 22nm node complementary metal-oxide semiconductor (CMOS),Journal of Applied Physics,2013,114(12)

    [2] Guilei Wang, Qiang Xu, Tao Yang, Jun Luo, Jinjuan Xiang, Jing Xu, Gaobo Xu, Chunlong Li, Junfeng Li, Jiang Yan, Chao Zhao, Dapeng Chen, Tianchun Ye,Application of atomic layer deposition Tungsten (ALD W) as gate filling metal for 22 nm and beyond nodes CMOS technology,ECS transaction, San Francisco,P317-324,2013. 。

    [3] Guilei Wang, Ahmad Abedin, Mahdi Moeen, Mohammadreza Kolahdouz, Jun Luo*, Yiluan Guo, Tao Chen, Huaxiang Yin, Huilong Zhu, Junfeng Li, Chao Zhao, Henry H Radamson,Integration of highly-strained SiGe materials in 14 nm and beyond nodes FinFET technology,Solid-StateElectronics,2015,103:222-228。

    [4] Guilei Wang, Qiang Xu, Tao Yang, Jinjuan Xiang, Jing Xu,Jianfeng Gao,Chunlong Li, Junfeng Li, Jiang Yan, Dapeng Chen, Tianchun Ye, Chao Zhao, Jun Luo,Application of Atomic Layer Deposition Tungsten (ALD W) as Gate Filling Metal for 22 nm and Beyond Nodes CMOS Technology,ECS Journal of Solid State Science and Technology,2014,3(4):P82-P85。

    [5] Guilei Wang, M Moeen, A Abedin, Yefeng Xu, Jun Luo, Yiluan Guo, Changliang Qin, Zhaoyun Tang, Haizhou Yin, Junfeng Li, Jiang Yan, Huilong Zhu, Chao Zhao, Dapeng Chen, Tianchun Ye, M Kolahdouz, Henry H Radamson. Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 22nm node pMOSFETs[J]. Solid-State Electronics, 2015, 114: 43-48.

    [6] Guilei Wang, Changliang Qin, Huaxiang Yin, Jun Luo, Ningyuan Duan, Ping Yang, Xingyu Gao, Tao Yang, Junfeng Li, Jiang Yan, Huilong Zhu, WenWu Wang, Dapeng Chen, Tianchun Ye, Chao Zhao, Henry H. Radamson. Study of SiGe selective epitaxial process integration with high-k and metal gate for 16/14nm nodes FinFET technology[J]. Microelectronic Engineering, 2016..

    [7] G. Wang, J. Luo, C. Qin, H. Cui, J. Liu, K. Jia, J. Li, T. Yang, H. Yin, C. Zhao, T. Ye, P. Yang, G. Jayakumar, H. H. Radamson. Integration of Selective Epitaxial Growth of SiGe/Ge Layers in 14nm Node FinFETs[J]. ECS Transactions, 2016, 75(8): 273-279.

    [8] Changliang Qin, Guilei Wang*, M. Kolahdouz, Jun Luo, Huaxing Yin, Ping Yang, Junfeng Li, Huilong Zhu, Zhao Chao, Tianchun Ye, Henry H. Radamson. Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 14nm node FinFETs[J]. Solid-State Electronics, 2016, 124: 10-15.

    [9] Guilei Wang, Jun Luo, Changliang Qin, Renrong Liang, Yefeng Xu, Jinbiao Liu, Junfeng Li, Huaxiang Yin, Jiang Yan, Huilong Zhu, Jun Xu, Chao Zhao, Henry H. Radamson and Tianchun Ye. Integration of Highly Strained SiGe in Source and Drain with HK and MG for 22 nm Bulk PMOS Transistors[J]. Nanoscale research letters, 2017, 12(1): 123.

    [10] Guilei Wang, Jun Luo, Jinbiao Liu, Tao Yang, Yefeng Xu, Junfeng Li, Huaxiang Yin, Jiang Yan, Huilong Zhu, Chao Zhao, Tianchun Ye and Henry H. Radamson. pMOSFETs Featuring ALD W Filling Metal Using SiH4 and B2H6 Precursors in 22 nm Node CMOS Technology[J]. Nanoscale Research Letters, 2017, 12(1): 306.

    [11] Henry H. Radamson*, Jun Luo, Changliang Qin, Huaxiang Yin, Huilong Zhu, Chao Zhao, Guilei Wang*.Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs[J]. International Journal of High Speed Electronics and Systems, 2017, 26(01n02): 1740003. Chapter. In book: Scaling and Integration of High Speed Electronics and Optomechanical Systems, pp.99-107

    专利申请:

  • 中国专利申请列表:

    1.王桂磊,尹海洲,半导体器件及其制造方法,201110029212.9

    2.王桂磊,李春龙,赵超,李俊峰,半导体器件及其制造方法,201110165241.8

    3.王桂磊,李春龙,赵超,李俊峰,半导体器件及其制造方法,201110165239.0

    4.王桂磊,李俊峰,赵超,消除接触孔工艺中桥接的方法,201110208407.X

    5.王桂磊,杨涛,一种提高浅沟槽隔离化学机械平坦化均匀性方法和设备,201110257878.X

    6.王桂磊,杨涛,李俊峰,赵超,一种提高浅沟槽隔离化学机械平坦化均匀性方法1,201110257855.9

    7.王桂磊,半导体器件及其制造方法,201110303593.5

    8.王桂磊,半导体器件及其制造方法,201110394014.2

    9.王桂磊,低温高覆盖性侧墙制造方法,201110433694.4

    10.王桂磊,崔虎山,赵超,半导体器件及其制造方法,201210162593.2

    11.王桂磊,李俊峰,赵超,半导体器件及其制造方法,201210273721.0

    12.王桂磊,李俊峰,赵超,半导体器件及其制造方法,201210345742.9

    13.王桂磊,杨涛,徐强,闫江,李俊峰,赵超 半导体器件及其制造方201210424681.5

    14.王桂磊,徐强,杨涛,闫江,李俊峰,赵超,半导体器件及其制造方法,201210473032.4

    15.王桂磊,秦长亮,李俊峰,赵超,氮化硅制造方法,201210473382.0

    16.王桂磊,朱慧珑,半导体器件制造方法,201310073320.5

    17.王桂磊,赵超,一种自然氧化层的去除方法,201310409612.1

    18.王桂磊,赵超,一种纯锗外延生长方法,201410081494.0

    19.王桂磊,赵超,徐强,杨涛, 一种半导体器件及其制造方法,201410089112.9

    20.王桂磊,赵超,徐强,陈韬,杨涛,李俊峰 一种半导体器件的制造方法,201410141701.7

    21.王桂磊,李俊峰,刘金彪,赵超,一种半导体器件的制造方法,201410196176.9

    22.王桂磊,崔虎山,殷华湘,李俊峰,朱慧珑,赵超, 半导体器件及其制造方法,201410328588.3

    23.王桂磊,殷华湘,赵超,半导体器件制造方法,201410328581.1

    24.王桂磊, 李俊峰,赵超,半导体器件制造方法,201410360703.5

    25.王桂磊, 李俊峰,赵超,半导体器件制造方法,201410360690.1

    26.王桂磊,崔虎山,殷华湘,李俊峰,朱慧珑,赵超,半导体器件及其制造方法,201410398357.X

    27.王桂磊,赵超,徐强,陈韬,杨涛,李俊峰,半导体器件及其制造方法,201410397828.5

    28.王桂磊,崔虎山,殷华湘,李俊峰,赵超,一种FinFet器件源漏外延前自然氧化层的去除方法,201410601934.0

    29.王桂磊,崔虎山,殷华湘,李俊峰,赵超,一种FinFet器件源漏外延前自然氧化层的去除方法,201410601931.7

    30.王桂磊,刘金彪,李俊峰,半导体器件制造方法,201410685729.7

    31.王桂磊,崔虎山,殷华湘,李俊峰,赵超,一种FinFet器件源漏外延设备及方法,201510028853.0

    32.王桂磊, 刘金彪,李俊峰,赵超, 半导体器件的制造方法 201510271246.7

    33.王桂磊, 刘金彪,高建峰,李俊峰,赵超,半导体器件的制造方法,201510351481.5

    34.王桂磊,Henry.H.Radamson,罗军,李俊峰,赵超,衬底及其制造方法,201510708606.5

    35.王桂磊,张严波,殷华湘,李俊峰,赵超,一种调节鳍体形貌的方法,201510708528.9

    36.王桂磊, Henry.H.Radamson,罗军,李俊峰,赵超, 衬底及其制造方法,201510708519.X

    国际专利申请列表:

    1.王桂磊,尹海洲,Semiconductor Device and Manufacturing Method thereof,13/320,581

    2.王桂磊,李春龙,赵超,SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, 13/497,744

    3.王桂磊,李俊峰,赵超,METHOD FOR ELIMINATING CONTACT BRIDGE IN CONTACT HOLE PROCESS,13/497,768

    4.王桂磊,李春龙,赵超,SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME,13/582,432

    5.王桂磊,SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME,13/582,433

    6.王桂磊,崔虎山; 赵超,SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME,13/878,524

    7.王桂磊,Semiconductor Device and Method for Manufacturing the Same,14/361,692

    8.王桂磊,刘金彪,李俊峰,METHODS FOR MANUFACURING SEMICONDUCTOR DEVICES,14/662,963

    9.王桂磊, 李俊峰, 刘金彪, 赵超,METHOD FOR MANUFACTURING SEMICONDUCNTOR DEVICE 14/698,624

    10.王桂磊, 刘金彪, 高建峰, 李俊峰, 赵超, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, 14/838,628

    获奖及荣誉:

  • 1.欧洲材料学研究会“青年科学家”奖

    2.中国科学院王守武奖学金优秀奖

    3.中国科学院院长优秀奖

    4.中国科学院大学三好标兵

    5.中国科学院澳门皇家赌场55533网址优秀员工